1. Field of the Invention
The present invention generally relates to integrated circuit technologies. More particularly, the present invention relates to a latch-up protection circuit for integrated circuits biased with multiple power supplies.
2. Description of the Related Art
Due to different voltage requirements of different integrated circuit (IC) generations, an IC chip may be powered by multiple power supplies at different voltage levels in consideration of multipurpose and compatibility. For example, the IC chip may have input/output circuitry to be powered by a voltage source of 5V while employing another voltage source of 3.3V to drive internal circuitry, such as memory cells and sense amplifiers.
As shown FIG. 1, a conventional CMOS circuit of an IC chip with multiple power supplies is schematically illustrated in a cross-sectional view. In the drawing, the conventional CMOS circuit is fabricated onto a p-type semiconductor substrate 10 in which an n-type well 20 is provided. The CMOS circuit is composed of a pMOS transistor and an nMOS transistor. The nMOS transistor includes two spaced-apart diffusion regions 12D and 12S as its drain and source, respectively, and a gate 14 overlying a portion of the p-type semiconductor substrate 10 therebetween. The pMOS transistor includes two spaced-apart diffusion regions 22D and 22S as its drain and source, respectively, and a gate 24 overlying a portion of the n-type well 20 therebetween.
Typically, the n-type well 20 is biased via a VDDH power rail. As shown in FIG. 1, the n-type well 20 is electrically connected to the VDDH power rail by an n+-type contact region 26. The p-type substrate 10 is electrically connected to a VSS power rail or a ground rail by a p+-type contact region 16. Because the IC chip is powered by anther power supply VDDL with a full level lower than that of the power supply VDDH, the pMOS transistor is configured with its source 22S connected to the VDDL power rail in order to ensure that the junction between the source 22S and the n-type well 20 keeps reverse-biased without causing leakage current.
However, in a CMOS circuit with multiple power supplies, those power supplies may reach their full levels at the different time after the IC chip is powered on. In a non-desirable power-on sequence, the power supply VDDL is established at the VDDL power rail sooner than the power supply VDDH does at the VDDH power rail. Thus, as shown in FIG. 2, a time interval T exists in which the potential of the VDDL power rail is temporarily greater than that of the VDDH power rail. Under these circumstances, the junction between the p+-type diffusion region 22S and the n-type well 20 is momentarily forward biased. Therefore, large current is conducted to flow through the n-type well 20 toward the n+-type contact region 26 so that a lateral semiconductor controlled rectifier, constituted by the p+-type diffusion region 22S, the n-type well 20, the p-type substrate 10, and the n+-type diffusion region 12S, may be triggered to latch-up.
Conventional approach employs a guard ring around the CMOS circuit to collect additional carriers and thus suppress latch-up. However, because there are numbers of the CMOS circuits biased with multiple power supplies to be integrated in the IC chip, the fact that each CMOS circuit should be enclosed by the associated guard ring takes up a great amount of precious chip area.
Alternatively, U.S. Pat. No. 4,871,927 employs an MOSFET to clamp the well potential within one relative threshold voltage from the source potential. However, this method is less efficient as the diffusion/well diode may also turn on at about the same time to inject carriers into the well and eventually causes latch-up in the CMOS circuit.
Therefore, it is an object of the present invention to provide a latch-up protection circuit for integrated circuits biased with multiple power supplies to prevent the CMOS circuitry from latch-up damage during a non-desirable power-on sequence.
For achieving the aforementioned object, the present invention provides a latch-up protection circuit integrated with a CMOS circuitry on a semiconductor substrate. The CMOS circuitry is powered by a first voltage and a second voltage via a first power rail and a second power rail, respectively. The latch-up protection circuit of the present invention comprises: a well of a first conductivity type, a first diffusion region of the first conductivity type, a second diffusion region of a second conductivity type, and a third diffusion region of the second conductivity type. The well is formed in the semiconductor substrate to establish a junction therebetween. The first diffusion region is formed in the well and connected to the first power rail. The second diffusion region is formed in the well and connected to the second power rail, where the second diffusion region is spaced from the junction by a first spacing. The third diffusion region is formed in the well and connected to a third power rail, where the third diffusion region is spaced from the second diffusion region by a second spacing smaller than the first spacing. Note that the third power rail can be a VSS power rail, a ground rail, or a power rail of other potential.
Accordingly, full levels at the first power rail and the second power rail can ensure that no latch-up triggering path exists in the CMOS circuitry during steady state (without external triggering source). However, a current is generated between the second diffusion region and the third diffusion region to reduce a potential difference between the first power rail and the second power rail when the first power rail has a temporary potential within those of the second power rail and the third power rail during a power-on sequence. Furthermore, There is a lateral bipolar junction transistor constituted with the well, the second diffusion region and the third diffusion region as its base, emitter and collector. The lateral BJT sinks the current provided by the second power rail if the potential of the first power rail is temporary within those of the second power rail and the third power rail. Therefore, the voltage rising of the first power rail is reduced to prevent latch-up event happening in the CMOS circuitry. Thus, the CMOS circuitry is protected without suffering from latch-up damage.